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// Your use of Intel Corporation's design tools, logic functions and other 
// software and tools, and its AMPP partner logic functions, and any output 
// files from any of the foregoing (including device programming or simulation 
// files), and any associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License Subscription 
// Agreement, Intel FPGA IP License Agreement, or other applicable 
// license agreement, including, without limitation, that your use is for the 
// sole purpose of programming logic devices manufactured by Intel and sold by 
// Intel or its authorized distributors.  Please refer to the applicable 
// agreement for further details.

`timescale 1ns / 1ps

module BncSecondaryTop
  (
   input  CLK_25M_OSC_SECONDARY_FPGA, //25Mhz input clock from board, to generate most of the internal clk freqs
   input  PWRGD_P1V2_MAX10_AUX_DPLD,  //this goes into PLL RST, so it is used to reset the whole logic as the PLL Lock output is the internal reset signal
   
   //I2C SLAVE (access thru MAIN-PLD, redirected to SECONDARY PLD thru this SMB link
   inout SMB_MAIN_DBG_MM_SCL,
   inout SMB_MAIN_DBG_MM_SDA,
   
   // SGPIO I/F between Main and Secondary FPGAs
   output SGPIO_MAIN_MOD_FPGA_CLK_R, 
   input  SGPIO_MAIN_MOD_FPGA_DIN,
   output SGPIO_MAIN_MOD_FPGA_DOUT_R,
   output SGPIO_MAIN_MOD_FPGA_LD_R_N,

   //CPU straps 
   // UPI
   output FM_CPU0_UPI0_AC_COUPLING_LVC1,
   output FM_CPU0_UPI1_AC_COUPLING_LVC1,
   
   output FM_CPU1_UPI0_AC_COUPLING_LVC1,
   output FM_CPU1_UPI1_AC_COUPLING_LVC1,

   // Rich One-Skt IO (R1S)
   output FM_CPU0_R1S_EN_LVC1,
   output FM_CPU1_R1S_EN_LVC1,

   //INTERPOSER
   input  FM_CPU0_INTRPSR_CABLE_PRSNT_LVC3,
   input  FM_CPU0_INTRPSR_RSVD0_LVC18,
   input  FM_CPU0_INTRPSR_RSVD1_LVC18,
   
   input  FM_CPU1_INTRPSR_CABLE_PRSNT_LVC3,
   input  FM_CPU1_INTRPSR_RSVD0_LVC18,
   input  FM_CPU1_INTRPSR_RSVD1_LVC18,

   //XTAL MODE
   input FM_CPU0_XTAL_MODE1_LVC1,
   input FM_CPU1_XTAL_MODE1_LVC1,

   //EXTERNAL CLK SEL
   input PU_CPU0_EXT_CLK_SEL_LVC1,
   input PU_CPU1_EXT_CLK_SEL_LVC1,

   //Debug Modes
   input FM_FORCE_PWRON_MODE1_LVC3,
   input FM_FORCE_PWRON_MODE2_LVC3,
   input FM_PLD_REV_N,
   input FM_BIOS_IMAGE_SWAP_RJC,
   input P3V3_BAT_SOURCE_RJC,

   input FM_CPU1_SKTOCC_BP,                    //CPU1 SKTOCC BYPASS
   input FM_VAL_DBG_JUMPER_EN_N,

   //LED Status & Control
   output LED_CONTROL_0,
   output LED_CONTROL_1,
   output LED_CONTROL_2,
   output LED_CONTROL_3,
   output LED_CONTROL_4,
   output LED_CONTROL_5,
   output LED_CONTROL_6,
   output LED_CONTROL_7,

   output FM_POST_7SEG1_SEL_N,
   output FM_POST_7SEG2_SEL_N,
   output FM_POSTLED_SEL,

   output FM_CPU0_DIMM_FAULT_LED_SEL_0_R,
   output FM_CPU0_DIMM_FAULT_LED_SEL_1_R,
   output FM_CPU1_DIMM_FAULT_LED_SEL_0_R,
   output FM_CPU1_DIMM_FAULT_LED_SEL_1_R,

   output FM_SKT0_FAULT_LED,
   output FM_SKT1_FAULT_LED,

   // CATERR
   output FM_CPU0_CATERR_N,
   output FM_CPU1_CATERR_N,

   
   // HEARTBEAT
   output FM_PLD_HEARTBEAT_LVC3,

   // THERMTRIP LATCHED
   output FM_THERMTRIP_CPU0_LED_LATCHED_R,
   output FM_THERMTRIP_CPU1_LED_LATCHED_R,

   //MISC CTRL & STATUS SIGNALS
   input  FM_PMBUS2_MUX_SEL_FPGA,
   output FM_PMBUS2_MUX_SEL,
   inout  FM_SPI_CPU0_MUX_SEL,
   inout  FM_TPM_CPU0_MUX_SEL,

   output FM_BIOS_POST_CMPLT_CPU0_R_N,
   output FM_BIOS_POST_CMPLT_CPU1_R_N,

   //SPEAKER
   output SPEAKER_BMC_R,

   input  FM_CPU0_GLB_RST_WARN_LVC18_N,
   output FM_CPU0_GLB_RST_WARN_FPGA_LVC18_N,

   input  FM_CPU1_REFCLK_RDY_R_OD,
   input  FM_CPU1_REFCLK_RDY_FPGA,

   inout  FM_CPU0_LEGACY_SKT_R,
   inout  FM_CPU1_LEGACY_SKT_R,

   inout  PD_CPU0_TXT_PLTEN_RJC,      
   inout  PD_CPU1_TXT_PLTEN_RJC,      
   inout  FM_CPU0_TXT_AGENT_LVC1,     
   inout  FM_CPU1_TXT_AGENT_LVC1,     
   inout  PU_CPU0_SAFE_MODE_BOOT_RJC, 
   inout  PU_CPU1_SAFE_MODE_BOOT_RJC, 
   inout  PD_CPU0_BIST_ENABLE_RJC,    
   inout  PD_CPU1_BIST_ENABLE_RJC,    
   inout  FP_CHASSIS_INTRUSION_RJC,   
   
   input  FM_CPU0_FRMAGENT_LVC1,
   input  FM_S5_WITH_12V_RJC_N,
   input  FM_I3C_SPD_R_SEL0,
   input  FM_I3C_SPD_R_SEL1,




   output PWRGD_CPU1_LVC1_R,     

   input  FM_CPU0_SKTOCC_RJC_N,

   input  FM_OCP_PERST_TIMING_SEL_LVC3,

   output FM_CPU0_PARTITION_ID1_LVC1,
   output FM_CPU1_PARTITION_ID1_LVC1,
  
   input  FM_DUAL_PARTITION_HDR_LVC25_N, 
   input  FM_RST_PERST_BIT3_LVC25,      
   input  FM_RST_PERST_BIT2_LVC25,       
   
   output FM_PARTITION_SEL_LVC3,       
   output FM_DUAL_PARTITION_LVC3_N,    
   output FM_DUAL_PARTITION_QS_LVC3_N,  
   
   inout SMB_HOST_SECFPGA_SCL,
   inout SMB_HOST_SECFPGA_SDA,
   inout FM_PCIE_FV_BIF_EN,// bifurcation pin enable
   
   input  FM_CPU1_PE3_MISC_MUX_SEL,
   inout  SMB_SEC_FPGA_DEBUG_SDA, 
   inout  SMB_SEC_FPGA_DEBUG_SCL, 

   output owOverrideValue_14,
   output owOverrideValue_15,
   output  [7:0] output_test,
   
   inout  FM_CPU0_DAM_R_LVC18,
   inout  FM_CPU1_DAM_R_LVC18

   
   );
    ////AVMM Master interface from BMC
    wire [31:0]  avmm_mst_addr;  
    wire         avmm_mst_read;  
    wire         avmm_mst_write;
    wire [31:0]  avmm_mst_wdata;
    wire [ 3:0]  avmm_mst_byteen;
    wire [31:0]  avmm_mst_rdata;
    wire         avmm_mst_rdvalid;
    wire         avmm_mst_waitrq;
       //--------------------------------
       //Local Parameter declarations
    
    //RJC CSR AVMM
    wire [31:0]  RJO_csr_address;
    wire         RJO_csr_write;
    wire [31:0]  RJO_csr_writedata;
    wire         RJO_csr_read;
    wire [31:0]  RJO_csr_readdata;
    wire         RJO_csr_readdatavalid;
    wire         RJO_csr_waitrequest;
    wire [ 3:0]  RJO_csr_byteenable;
	wire         invalid_access_rjo;
    
    //I2C AVMM
    wire [31:0]  secondary_csr_address;
    wire         secondary_csr_write;
    wire [31:0]  secondary_csr_writedata;
    wire         secondary_csr_read;
    wire [31:0]  secondary_csr_readdata;
    wire         secondary_csr_readdatavalid;
    wire         secondary_csr_waitrequest;
    wire [ 3:0]  secondary_csr_byteenable;
   
   localparam SGPIO_SEC2MOD = 20;   
   
   
   //WIRES

   wire wClk_2M, wClk_20M, wClk_100M,wClk_50M;     //internally generated CLKs by internal PLL from the external 25MHz clk source
   wire wRst_n;                           //pll-lock output signal used as our internal reset signal (active low)

   
   //SGPIO between Secondary and Main PLDs
   
   wire [(SGPIO_SEC2MOD*8)-1:0] wIPData;
   wire [(SGPIO_SEC2MOD*8)-1:0] wOPData;
   wire                         wSec2MainValid;     //for sgpio data valid

   wire                         wRstPltrstSyncPfrOutAck_n;
   wire                         wPltRstCpu0;
   wire                         wPltRstCpu1;
   wire                         wBmcOnctlAck_n; 
   wire                         wBmcOnctlSync_n;
   wire                         wNodeID1;
   wire                         wNodeID0;
   wire                         w4S_8SMode_n;
   wire                         wStandAloneMode_n;
   wire                         wHPfrEna;
   wire                         wLegacyNode;
   wire                         wPfrGlobalAck;
   wire                         wModularPrsnt;
   wire                         wSMRJODone;
   wire                         wSMPldUpgradeAck;
   wire                         wSMPldUpgradeSync;
   wire                         wMCpu1PartitionId1;
   wire                         wMCpu1PartitionId0;
   wire                         wMCpu0PartitionId1;
   wire                         wMCpu0PartitionId0;                        
       

   wire                         wDualPartition_n;
   wire                         wPartitionSel;
   wire                         wIsModular;
   wire [7:0]                   wMainRev;
   wire [7:0]                   wMainTestRev;
   wire [7:0]                   wScmRev;
   wire [7:0]                   wScmTestRev;
   wire [7:0]                   wStatusLED;
   wire                         wScmBmcAuxPwrFlt;
   wire                         wCpuAuxPwrFlt;
   wire                         wScmAuxPwrFlt;
   wire                         wBmcPwrFlt;
   wire                         wPfrOverride_n;
   wire                         wCpu0BiosPostCmplt_n;
   wire                         wCpu1BiosPostCmplt_n;
   wire                         wUpiInitDone;
   
   wire [3:0]                   wMasterCode;
   wire [2:0]                   wPsuFltCode;
   wire                         wP5VMainPwrFlt;
   wire [7:0]                   wBiosPostCode;
   wire [7:0]                   wPfrPostCode_n;
   
   wire [5:0]                   wCpu0DimmFltCode;   
   wire [5:0]                   wCpu1DimmFltCode;
   
   wire [7:0]                   wCpu0FltCode;
   wire [7:0]                   wCpu1FltCode;

   wire [7:0]                   wLedCpu0DimmCh1_8Flt;
   wire [7:0]                   wLedCpu1DimmCh1_8Flt;


   wire [44:0]                  wSources;
   
   wire                         wCpu0LegacySktOvrrd;
   wire                         wCpu1LegacySktOvrrd;
   wire                         wCpu0R1sEnOvrrd;
   wire                         wCpu1R1sEnOvrrd;
   wire                         wSgpioMainModClkOvrrd;
   wire                         wSgpioMainModDoutOvrrd;
   wire                         wSgpioMainModLdNOvrrd;
   wire                         wCpu0PartitionId1Ovrrd;
   wire                         wCpu1PartitionId1Ovrrd;
   wire                         wBiosImageSwapOvrrd;
   wire                         wSpiCpu0MuxSelOvrrd;
   wire                         wPmbus2MuxSelOvrrd;
   wire                         wTpmCpu0MuxSelOvrrd;
   wire                         wSmbFpgaNvmeAlertNOvrrd;
   wire                         wCpu0SktOccOvrrd;
   wire                         wCpu1SktOccOvrrd;

   wire                         wCpu0Upi0AcCouplingOvrrd;
   wire                         wCpu0Upi1AcCouplingOvrrd;
   wire                         wCpu1Upi0AcCouplingOvrrd;
   wire                         wCpu1Upi1AcCouplingOvrrd;
   
   wire i2c_dbg_data_in   ; 
   wire i2c_dbg_clk_in    ; 
   wire i2c_dbg_data_oe   ; 
   wire i2c_dbg_clk_oe    ; 
   
   wire wDualPartition_QS;
   wire wREV_ID0, wREV_ID1, wREV_ID2;
   wire i2c_pca_data_in   ; 
   wire i2c_pca_clk_in    ; 
   wire i2c_pca_data_oe   ; 
   wire i2c_pca_clk_oe    ; 

   //Bifurcations wires
   wire wF0M_CPU0_EDSFFX4_EXPCARD_IO0_LVC3_R ;     
   wire wFM_CPU1_RIGHT_RISER_WIDTH_LVC18     ;        
   wire wFM_CPU1_RIGHT_RISER_MODE_LVC18_N    ;       
   wire wFM_CPU0_LEFT_RISER_WIDTH_LVC18_N    ;       
   wire wFM_CPU0_LEFT_RISER_MODE_LVC18_N     ; 
   
   localparam JUMPER_COUNT    = 6'd48;
   integer j;
   wire  [JUMPER_COUNT-1:0]    wOverrideValue  ;  // wire ovelue overrided
   wire  [JUMPER_COUNT-1:0]    wCurrentValue   ;  // value overrided or value direct of pin
   //wire  [JUMPER_COUNT-1:0]    CurrentValue    ;  // value overrided or value direct of pin
   wire  [JUMPER_COUNT-1:0]    Jumper          ;  // wire of physical pin
   wire  [JUMPER_COUNT+12-1:0] wOvEnable_n     ;  // override is enable in low level

   //****Wires FOR RJO **************************************************** 
   //wire   wFM_RJO_ENA_N;
   
   //inout
   wire   wPD_CPU0_TXT_PLTEN_RJC;
   wire   wPD_CPU1_TXT_PLTEN_RJC;
   wire   wPD_CPU0_BIST_ENABLE_RJC;
   wire   wPD_CPU1_BIST_ENABLE_RJC;
   wire   wFP_CHASSIS_INTRUSION_RJC;
   wire   wFM_CPU0_TXT_AGENT_LVC1;
   wire   wFM_CPU1_TXT_AGENT_LVC1;
   wire   wPU_CPU0_SAFE_MODE_BOOT_RJC;
   wire   wPU_CPU1_SAFE_MODE_BOOT_RJC;

   
   wire   wFM_BIOS_IMAGE_SWAP_RJC;
   wire   wFM_FORCE_PWRON_MODE1_LVC3;
   wire   wFM_FORCE_PWRON_MODE2_LVC3;
   wire   wFM_S5_WITH_12V_RJC_N;
   wire   wP3V3_BAT_SOURCE_RJC;
   wire   wFM_CPU0_SKTOCC_RJC_N;
   wire   wFM_CPU1_SKTOCC_BP;
   wire   wFM_OCP_PERST_TIMING_SEL_LVC3;
   wire   wFM_PMBUS2_MUX_SEL_FPGA;
   
   
   //*** Wires for Bifurcation *********************************************
	wire [7:0]bidin;
	wire [7:0]bidout;
   wire [7:0]wAddress;
   wire [7:0]wData_out;
   
   // wire used in flash avmm intf--RJO
   wire          RJO_flash_csr_addr 	         ;          
   wire          RJO_flash_csr_read             ;           
   wire [31: 0]  RJO_flash_csr_writedata        ;      
   wire          RJO_flash_csr_write            ;          
   wire [31: 0]  RJO_flash_csr_readdata         ;      
   wire [31: 0]  RJO_flash_data_addr            ;          
   wire          RJO_flash_data_read            ;          
   wire [31: 0]  RJO_flash_data_writedata       ;     
   wire          RJO_flash_data_write           ;         
   wire [31: 0]  RJO_flash_data_readdata        ;      
   wire          RJO_flash_data_waitrequest     ;   
   wire          RJO_flash_data_readdatavalid   ; 
   wire [ 6: 0]  RJO_flash_data_burstcount      ;   
   
   
   wire wAUX_PWRGD_CPU0;
   wire wCPU_RST_CPU0;
   
   // wires
   wire wPLTRST_N, wSlpS3, wAUX_PWRGD_CPU, iCPU0_MEM_Done, iCPU1_MEM_Done;
   wire PFR_FORCE_RECOVERY_RJC_N_Value, PFR_DEBUG_JUMPER_RJC_N_Value, FM_TTK_SPI_EN_RJC_N_Value, PFR_FORCE_RECOVERY_RJC_N_Override, PFR_DEBUG_JUMPER_RJC_N_Override, FM_TTK_SPI_EN_RJC_N_Override;
   
   wire T_Reset;
   
   wire wCpu0LegacySktSel     ;
   wire wCpu1LegacySktSel     ;
   wire wCpu0R1sEnSel         ;
   wire wCpu1R1sEnSel         ;
   wire wSgpioMainModClkSel   ;
   wire wSgpioMainModDoutSel  ;
   wire wSgpioMainModLdNSel   ;
   wire wCpu0PartitionIdSel   ;
   wire wCpu1PartitionIdSel   ;
   wire wBiosImageSwapSel     ;
   wire wSpiCpu0MuxSelSel     ;
   wire wPmbus2MuxSelSel      ;
   wire wTpmCpu0MuxSelSel     ;
   wire wSmbFpgaNvmeAlertNSel ;
   wire wCpu0SktOccSel        ;
   wire wCpu1SktOccSel        ;
   
   wire wCpu0Upi0AcCouplingSel;
   wire wCpu0Upi1AcCouplingSel;
   wire wCpu1Upi0AcCouplingSel;
   wire wCpu1Upi1AcCouplingSel;
   
   
   
   
   
   
   
   ///// ASSIGNS  /////
   
   assign wCpu0LegacySktSel      = wSources[44];
   assign wCpu1LegacySktSel      = wSources[42];
   assign wCpu0R1sEnSel          = wSources[40];
   assign wCpu1R1sEnSel          = wSources[38];
   assign wSgpioMainModClkSel    = wSources[36];
   assign wSgpioMainModDoutSel   = wSources[34];
   assign wSgpioMainModLdNSel    = wSources[32];
   assign wCpu0PartitionIdSel    = wSources[30];
   assign wCpu1PartitionIdSel    = wSources[28];
   assign wBiosImageSwapSel      = wSources[26];
   assign wSpiCpu0MuxSelSel      = wSources[24];
   assign wPmbus2MuxSelSel       = wSources[22];
   assign wTpmCpu0MuxSelSel      = wSources[20];
   assign wSmbFpgaNvmeAlertNSel  = wSources[18];
   assign wCpu0SktOccSel         = wSources[16];
   assign wCpu1SktOccSel         = wSources[14];

   assign wCpu0Upi0AcCouplingSel = wSources[12];
   assign wCpu0Upi1AcCouplingSel = wSources[10];
   assign wCpu1Upi0AcCouplingSel = wSources[8];
   assign wCpu1Upi1AcCouplingSel = wSources[6];
   //PLL

   // generate clock and reset from external clock input
   pll_debug pll_debug_inst 
   (
    .areset (~PWRGD_P1V2_MAX10_AUX_DPLD), //We use this pwrgd as the reset for the PLL
    .inclk0 (CLK_25M_OSC_SECONDARY_FPGA), //input clock from CLK GEN at 25MHz
    .c0     (wClk_2M),   //2MHz
    .c1     (wClk_20M),  //20MHz
    .c2     (wClk_100M), //100MHz
    .c3     (wClk_50M),  //50MHz
    .locked (wRst_n)     // reset signal
    );
   
   ////////////////////////////////////////////////////////////////////////////////////
   assign wRstPltrstSyncPfrOutAck_n = wPltRstCpu0;
   assign wBmcOnctlAck_n = wBmcOnctlSync_n;

   assign wNodeID1          = 1'b0;
   assign wNodeID0          = 1'b0;
   assign w4S_8SMode_n      = 1'b0;
   assign wStandAloneMode_n = 1'b0;
   assign wHPfrEna          = 1'b0;
   assign wLegacyNode       = 1'b1;
   assign wPfrGlobalAck     = 1'b0;
   assign wModularPrsnt     = 1'b0;

   assign wMCpu1PartitionId1 = 1'b0;
   assign wMCpu1PartitionId0 = 1'b0;
   assign wMCpu0PartitionId1 = 1'b0;
   assign wMCpu0PartitionId0 = 1'b0;

   assign wIPData[49] = FM_PCIE_FV_BIF_EN;

   assign wIPData[46] = FM_DUAL_PARTITION_HDR_LVC25_N;
   assign wIPData[45] = FM_RST_PERST_BIT3_LVC25;

   assign wIPData[42] = wSMPldUpgradeAck;
   assign wIPData[41] = wFM_CPU1_SKTOCC_BP;
   assign wIPData[40] = FM_PLD_REV_N;

   assign wIPData[31] = wMCpu1PartitionId1;
   assign wIPData[30] = wMCpu1PartitionId0;
   assign wIPData[29] = wMCpu0PartitionId1;
   assign wIPData[28] = wMCpu0PartitionId0;
   
   assign wIPData[27] = wRstPltrstSyncPfrOutAck_n;
   assign wIPData[26] = wBmcOnctlAck_n;
   assign wIPData[25] = wNodeID1;
   assign wIPData[24] = wNodeID0;
   assign wIPData[23] = w4S_8SMode_n;
   assign wIPData[22] = wStandAloneMode_n;
   assign wIPData[21] = wHPfrEna;
   assign wIPData[20] = wLegacyNode;
   assign wIPData[19] = wPfrGlobalAck;
   assign wIPData[18] = wModularPrsnt;
   assign wIPData[17] = FM_CPU1_INTRPSR_RSVD1_LVC18;
   assign wIPData[16] = FM_CPU1_INTRPSR_RSVD0_LVC18;
   assign wIPData[15] = FM_CPU1_INTRPSR_CABLE_PRSNT_LVC3;
     
   assign wIPData[14:11] = 4'b0000;

   assign wIPData[10] = wOPData[7];             
                                                    
   assign wIPData[9] = wFM_BIOS_IMAGE_SWAP_RJC;
   assign wIPData[8] = wSMRJODone;
   
   assign wIPData[7] = FM_CPU0_INTRPSR_RSVD1_LVC18;
   assign wIPData[6] = FM_CPU0_INTRPSR_RSVD0_LVC18;
   assign wIPData[5] = FM_CPU0_INTRPSR_CABLE_PRSNT_LVC3;
   
   assign wIPData[4] = wFM_OCP_PERST_TIMING_SEL_LVC3;       
                                                          
   assign wIPData[3] = wFM_FORCE_PWRON_MODE1_LVC3;       
   assign wIPData[2] = wFM_S5_WITH_12V_RJC_N ;
   assign wIPData[1] = FM_VAL_DBG_JUMPER_EN_N;               //Remote Jumper Enable
   assign wIPData[0] = 1'b0;                            

   
   master_ngsx #(.BYTE_REGS(SGPIO_SEC2MOD))
   SgpioSec2MainPlds (
                      .iRst_n(wRst_n),
                      .iClk(wClk_2M),
                      .iEna(1'b1),                                  
                      .oLoad_n(SGPIO_MAIN_MOD_FPGA_LD_R_N),
                      .iPData(wIPData),
                      .oSData(SGPIO_MAIN_MOD_FPGA_DOUT_R),
                      .iSData(SGPIO_MAIN_MOD_FPGA_DIN),
                      .oClk(SGPIO_MAIN_MOD_FPGA_CLK_R),
                      .oPData(wOPData)
                      );
   
   
   assign wSec2MainValid                       = !wOPData[0];                                 //comes as active low from sgpio, as inverted, becomes active high
   assign FM_PLD_HEARTBEAT_LVC3                = wOPData[1] && wSec2MainValid;              //byte 0
   assign wDualPartition_n                     = wOPData[2] && wSec2MainValid;
   assign wPartitionSel                        = wOPData[3] && wSec2MainValid;
   assign wIsModular                           = wOPData[4] && wSec2MainValid;
   assign wPltRstCpu0                          = wOPData[5] && wSec2MainValid;
   assign wBmcOnctlSync_n                      = wOPData[6] && wSec2MainValid;
   //                                                               [7]
   assign wMainRev                             = wSec2MainValid ? wOPData[15:8]  : 8'h00;   //byte 1
   assign wMainTestRev                         = wSec2MainValid ? wOPData[23:16] : 8'h00;   //byte 2
   assign wScmRev                              = wSec2MainValid ? wOPData[31:24] : 8'h00;   //byte 3
   assign wScmTestRev                          = wSec2MainValid ? wOPData[39:32] : 8'h00;   //byte 4
   assign wStatusLED                           = wSec2MainValid ? wOPData[47:40] : 8'h00;   //byte 5
										       
   assign wScmBmcAuxPwrFlt                     = wOPData[48] && wSec2MainValid;             //byte 6
   assign wCpuAuxPwrFlt                        = wOPData[49] && wSec2MainValid;
   assign wScmAuxPwrFlt                        = wOPData[50] && wSec2MainValid;
   assign wBmcPwrFlt                           = wOPData[51] && wSec2MainValid;
   assign wPfrOverride_n                       = wOPData[52] && wSec2MainValid;
   assign wCpu0BiosPostCmplt_n                 = wOPData[53] && wSec2MainValid;
   assign wCpu1BiosPostCmplt_n                 = wOPData[54] && wSec2MainValid;
   assign wUpiInitDone                         = wOPData[55] && wSec2MainValid;
										       
   assign wMasterCode                          = wSec2MainValid ? wOPData[59:56] : 4'h0;    //byte 7
   assign wPsuFltCode                          = wSec2MainValid ? wOPData[62:60] : 3'h0;                        
   assign wP5VMainPwrFlt                       = wOPData[63] && wSec2MainValid;
   assign wBiosPostCode                        = wSec2MainValid ? wOPData[71:64] : 8'h00;   //byte 8
   assign wPfrPostCode_n                       = wSec2MainValid ? wOPData[79:72] : 8'h00;   //byte 9
										       
   assign wCpu0DimmFltCode                     = wSec2MainValid ? wOPData[85:80] : 6'h00;   //byte 10
   
   assign wAUX_PWRGD_CPU0                      = wSec2MainValid ? wOPData[86] : 1'h0;
										       
   assign wCpu1DimmFltCode                     = wSec2MainValid ? wOPData[93:88] : 6'h00;   //byte 11
   //                                                               [95:94]
										       
   assign wCpu0FltCode                         = wSec2MainValid ? wOPData[103:96] : 8'h00;  //byte 12
   assign wCpu1FltCode                         = wSec2MainValid ? wOPData[111:104] : 8'h00; //byte 13
										       
   assign wLedCpu0DimmCh1_8Flt                 = wSec2MainValid ? wOPData[119:112] : 8'h00; //byte 14
   assign wLedCpu1DimmCh1_8Flt                 = wSec2MainValid ? wOPData[127:120] : 8'h00; //byte 15
										       
   assign FM_CPU0_CATERR_N                     = wSec2MainValid ? wOPData[128] : 1'b1;            //byte 16
   assign FM_CPU1_CATERR_N                     = wSec2MainValid ? wOPData[129] : 1'b1;
   assign FM_THERMTRIP_CPU0_LED_LATCHED_R      = wSec2MainValid ? wOPData[130] : 1'b0;
   assign FM_THERMTRIP_CPU1_LED_LATCHED_R      = wSec2MainValid ? wOPData[131] : 1'b0;
   assign FM_SKT0_FAULT_LED                    = wOPData[133] && wSec2MainValid;
   assign FM_SKT1_FAULT_LED                    = wOPData[134] && wSec2MainValid;
										       
   assign PWRGD_CPU1_LVC1_R                    = wSec2MainValid && wOPData[137];
   assign wSMPldUpgradeSync                    = wOPData[138] && wSec2MainValid;
										       
   assign wDualPartition_QS                    = wOPData[143] && wSec2MainValid;
   assign wCPU_RST_CPU0                        = wOPData[144] && wSec2MainValid;//bit 144 to control Partition_ID in Secondary FPGA
   assign wPltRstCpu1                          = wOPData[145] && wSec2MainValid;
										       
   assign wREV_ID0                             = wOPData[146] && wSec2MainValid;
   assign wREV_ID1                             = wOPData[147] && wSec2MainValid;
   assign wREV_ID2                             = wOPData[148] && wSec2MainValid;
										       
   
   assign wFM_CPU0_LEFT_RISER_MODE_LVC18_N     = wOPData[150] && wSec2MainValid;//bifurcation 
   assign wFM_CPU0_LEFT_RISER_WIDTH_LVC18_N    = wOPData[151] && wSec2MainValid;//bifurcation 
   assign wFM_CPU1_RIGHT_RISER_MODE_LVC18_N    = wOPData[152] && wSec2MainValid;//bifurcation 
   assign wFM_CPU1_RIGHT_RISER_WIDTH_LVC18     = wOPData[153] && wSec2MainValid;//bifurcation 
   assign wF0M_CPU0_EDSFFX4_EXPCARD_IO0_LVC3_R = wOPData[154] && wSec2MainValid;//bifurcation 
  

   
   
   ////////////////////////////////////////////////////////////////////////////////////

   
   
   BncSecondary BncSecondary
   (
    .iRst_n(wRst_n),
    .iClk_2M(wClk_2M),                                                              //clk @ 2MHz
    .iClk_20M(wClk_20M),                                                            //clk @ 20MHz

    .iFmPldRev_n(FM_PLD_REV_N),

    //LED Status & Control
    .iPltRstCpu0(wPltRstCpu0),
    .iMainRev(wMainRev),
    .iMainTestRev(wMainTestRev),
    .iScmRev(wScmRev),
    .iScmTestRev(wScmTestRev),
    .iStatusLED(wStatusLED),
    .iScmBmcAuxPwrFlt(wScmBmcAuxPwrFlt),
    .iScmAuxPwrFlt(wScmAuxPwrFlt),
    .iCpuAuxPwrFlt(wCpuAuxPwrFlt),
    .iBmcPwrFlt(wBmcPwrFlt),
    .iPfrOverride_n(wPfrOverride_n),
    .iMasterCode(wMasterCode),
    .iPsuFltCode(wPsuFltCode),
    .iP5VMainPwrFlt(wP5VMainPwrFlt),
    .iBiosPostCode(wBiosPostCode),
    .iPfrPostCode_n(wPfrPostCode_n),  
    .iCpu0DimmFltCode(wCpu0DimmFltCode),
    .iCpu1DimmFltCode(wCpu1DimmFltCode),
    .iCpu0FltCode(wCpu0FltCode),
    .iCpu1FltCode(wCpu1FltCode),
    .iLedCpu0DimmCh1_8Flt(wLedCpu0DimmCh1_8Flt),
    .iLedCpu1DimmCh1_8Flt(wLedCpu1DimmCh1_8Flt),
    
    .oLedCtrl0(LED_CONTROL_0),
    .oLedCtrl1(LED_CONTROL_1),
    .oLedCtrl2(LED_CONTROL_2),
    .oLedCtrl3(LED_CONTROL_3),
    .oLedCtrl4(LED_CONTROL_4),
    .oLedCtrl5(LED_CONTROL_5),
    .oLedCtrl6(LED_CONTROL_6),
    .oLedCtrl7(LED_CONTROL_7),

    .oFmPost7Seg1Sel_n(FM_POST_7SEG1_SEL_N),
    .oFmPost7Seg2Sel_n(FM_POST_7SEG2_SEL_N),
    .oFmPostLedSel(FM_POSTLED_SEL),

    .oFmCpu0DimmFaultLedSel0(FM_CPU0_DIMM_FAULT_LED_SEL_0_R),
    .oFmCpu0DimmFaultLedSel1(FM_CPU0_DIMM_FAULT_LED_SEL_1_R),
    .oFmCpu1DimmFaultLedSel0(FM_CPU1_DIMM_FAULT_LED_SEL_0_R),
    .oFmCpu1DimmFaultLedSel1(FM_CPU1_DIMM_FAULT_LED_SEL_1_R),

    //MISC CTRL & STATUS SIGNALS
    .iFmPmbus2MuxSelFpga(wFM_PMBUS2_MUX_SEL_FPGA),
    .oFmPmbus2MuxSel(FM_PMBUS2_MUX_SEL),

    //IBL
    .iFmCpu0GlbRstWarn_n(FM_CPU0_GLB_RST_WARN_LVC18_N),
    .oFmCpu0GlbRstWarn_n(FM_CPU0_GLB_RST_WARN_FPGA_LVC18_N),
	
	.oFmCpu0PartitionId(FM_CPU0_PARTITION_ID1_LVC1), //For Partition_ID logic
	.iAuxPwrgdCpu0(wAUX_PWRGD_CPU0) //For Partition_ID logic
	 
    );
   

   
   assign FM_CPU0_UPI0_AC_COUPLING_LVC1 = 1'bZ;
   assign FM_CPU0_UPI1_AC_COUPLING_LVC1 = 1'bZ;
   assign FM_CPU1_UPI0_AC_COUPLING_LVC1 = 1'bZ;
   assign FM_CPU1_UPI1_AC_COUPLING_LVC1 = 1'bZ;
   
   assign FM_CPU0_R1S_EN_LVC1           = 1'b0;
   assign FM_CPU1_R1S_EN_LVC1           = 1'b0;
   
   assign FM_SPI_CPU0_MUX_SEL           = 1'bZ;
   assign FM_TPM_CPU0_MUX_SEL           = 1'bZ;

   assign FM_BIOS_POST_CMPLT_CPU0_R_N = wCpu0BiosPostCmplt_n;
   assign FM_BIOS_POST_CMPLT_CPU1_R_N = wCpu1BiosPostCmplt_n;

   //LEGACY SKT signals
   assign FM_CPU0_LEGACY_SKT_R          = 1'bZ;
   assign FM_CPU1_LEGACY_SKT_R          = 1'bZ;

   assign FM_CPU1_PARTITION_ID1_LVC1    = wPltRstCpu1 ? 1'bZ : 1'b0;    
   
   assign wFM_BOARD_REV_ID = {wREV_ID2, wREV_ID1, wREV_ID0};

   assign FM_PARTITION_SEL_LVC3       = wPartitionSel;    
   assign FM_DUAL_PARTITION_LVC3_N    = wDualPartition_n; 
   assign FM_DUAL_PARTITION_QS_LVC3_N = wDualPartition_QS;
   
   
   /////////////////////////////////////////////////////////////////
   /////////////////////////This i2c_slave is connected to BMC
assign SMB_MAIN_DBG_MM_SDA   = i2c_dbg_data_oe ? 1'b0 : 1'bz;

assign SMB_MAIN_DBG_MM_SCL   = i2c_dbg_clk_oe ? 1'b0 : 1'bz;
   /////////////////////////This i2c_slave is connected to PCA
assign i2c_pca_data_in       = SMB_HOST_SECFPGA_SDA;
assign SMB_HOST_SECFPGA_SDA   = i2c_pca_data_oe ? 1'b0 : 1'bz;
assign i2c_pca_clk_in        = SMB_HOST_SECFPGA_SCL;
assign SMB_HOST_SECFPGA_SCL   = i2c_pca_clk_oe ? 1'b0 : 1'bz;


// signals of i2c slave that come of fpga main. it convert to i2c to avmm protocol
i2c_slave_dbg_wrapper i2c_slave_dbg_wrapper_secondary_inst
(
   .clk                       ( wClk_20M                  ),												
   .rst_n                     ( wRst_n                    ), 											

   //IIC interface
   .i2c_data_in               ( i2c_dbg_data_in          ),
   .i2c_clk_in                ( i2c_dbg_clk_in           ),
   .i2c_data_oe               ( i2c_dbg_data_oe          ),
   .i2c_clk_oe                ( i2c_dbg_clk_oe           ),
   
   //AVMM interface	
	.waitrequest               ( avmm_mst_waitrq          ),
	.readdatavalid             ( avmm_mst_rdvalid         ),
	.readdata                  ( avmm_mst_rdata           ),
	
	.address                   ( avmm_mst_addr            ),
	.write                     ( avmm_mst_write           ),
	.writedata                 ( avmm_mst_wdata           ),
	.read                      ( avmm_mst_read            ),
	.byteenable                ( avmm_mst_byteen          ),
	
	//error report
	.invalid_access            ( invalid_access_dbg       )
);


//mux for switch to avmm  multi slave.
avmm_mux_1to2_with_err_report 
   #(
    .SLV1_ADDR_LOW  ( 32'h0000 ),
    .SLV1_ADDR_High ( 32'h00FF ),
    .SLV2_ADDR_LOW  ( 32'h0100 ),
    .SLV2_ADDR_High ( 32'h01FF )   
   ) 
avmm_mux_1to2_bmc_inst 
(
    .clk                 ( wClk_20M                        ),
    .rst_n               ( wRst_n                          ),
    //AVMM_Single_Master, connected to I2C slave AVMM
    .mst_address         ( avmm_mst_addr                   ),
    .mst_write           ( avmm_mst_write                  ),
    .mst_writedata       ( avmm_mst_wdata                  ),          
    .mst_read            ( avmm_mst_read                   ),          
    .mst_readdata        ( avmm_mst_rdata                  ),      
    .mst_readdatavalid   ( avmm_mst_rdvalid                ), 
    .mst_waitrequest     ( avmm_mst_waitrq                 ),
    .mst_byteenable      ( avmm_mst_byteen                 ),
    .invalid_access      ( invalid_access_dbg              ),	 
    //AVMM_Slave_1, connect to secondary global csr        
    .slv1_address        ( secondary_csr_address           ),
    .slv1_write          ( secondary_csr_write             ),
    .slv1_writedata      ( secondary_csr_writedata         ),          
    .slv1_read           ( secondary_csr_read              ),          
    .slv1_readdata       ( secondary_csr_readdata          ),      
    .slv1_readdatavalid  ( secondary_csr_readdatavalid     ), 
    .slv1_waitrequest    ( secondary_csr_waitrequest       ),
    .slv1_byteenable     ( secondary_csr_byteenable        ),
	 .invalid_access_slv1 ( invalid_access_glb              ),
    //AVMM_Slave_2, connect to remote jumper control csr
    .slv2_address        (  RJO_csr_address                ),
    .slv2_write          (  RJO_csr_write                  ),
    .slv2_writedata      (  RJO_csr_writedata              ),          
    .slv2_read           (  RJO_csr_read                   ),          
    .slv2_readdata       (  RJO_csr_readdata               ),      
    .slv2_readdatavalid  (  RJO_csr_readdatavalid          ), 
    .slv2_waitrequest    (  RJO_csr_waitrequest            ),            
    .slv2_byteenable     (  RJO_csr_byteenable             ),
	.invalid_access_slv2 (  invalid_access_rjo             )
);

   
   assign  wCurrentValue[1 ]  =  PD_CPU0_TXT_PLTEN_RJC        ; //    pin rjo #1  address = 0x10  // inout 
   assign  wCurrentValue[2 ]  =  PD_CPU1_TXT_PLTEN_RJC        ; //    pin rjo #2  address = 0x14  // inout
   assign  wCurrentValue[3 ]  =  PD_CPU0_BIST_ENABLE_RJC      ; //    pin rjo #3  address = 0x18  // inout
   assign  wCurrentValue[4 ]  =  PD_CPU1_BIST_ENABLE_RJC      ; //    pin rjo #4  address = 0x1C  // inout
		                        
   assign  wCurrentValue[5 ]  =  FM_BIOS_IMAGE_SWAP_RJC       ; //    pin rjo #5  address = 0x20
   assign  wCurrentValue[6 ]  =  FM_FORCE_PWRON_MODE1_LVC3    ; //    pin rjo #6  address = 0x24 
   assign  wCurrentValue[7 ]  =  FM_FORCE_PWRON_MODE2_LVC3    ; //    pin rjo #7  address = 0x28
   assign  wCurrentValue[8 ]  =  FM_S5_WITH_12V_RJC_N         ; //    pin rjo #8  address = 0x2C  
   assign  wCurrentValue[9 ]  =  P3V3_BAT_SOURCE_RJC          ; //    pin rjo #9  address = 0x30 // only read
   assign  wCurrentValue[10]  =  FM_CPU0_SKTOCC_RJC_N         ; //    pin rjo #10 address = 0x34 // only read 
   assign  wCurrentValue[11]  =  FM_CPU1_SKTOCC_BP            ; //    pin rjo #11 address = 0x38 // only read 
		                        
   assign  wCurrentValue[12]  =  FP_CHASSIS_INTRUSION_RJC     ; //    pin rjo #12 address = 0x3C  // inout
		                        
   assign  wCurrentValue[13]  =  FM_OCP_PERST_TIMING_SEL_LVC3 ; //    pin rjo #13 address = 0x40 
		                        
   assign  wCurrentValue[14]  =  FM_CPU0_TXT_AGENT_LVC1       ; //    pin rjo #14 address = 0x44  // inout 
   assign  wCurrentValue[15]  =  FM_CPU1_TXT_AGENT_LVC1       ; //    pin rjo #15 address = 0x48  // inout 
   assign  wCurrentValue[16]  =  PU_CPU0_SAFE_MODE_BOOT_RJC   ; //    pin rjo #16 address = 0x4C  // inout 
   assign  wCurrentValue[17]  =  PU_CPU1_SAFE_MODE_BOOT_RJC   ; //    pin rjo #17 address = 0x50  // inout 
		                        
   assign  wCurrentValue[18]  =  FM_PMBUS2_MUX_SEL_FPGA       ; //    pin rjo #18 address = 0x54
		                        
   assign  wCurrentValue[46]  =  FM_CPU0_DAM_R_LVC18          ; //    pin rjo #19 address = 0xC4  // inout 
   assign  wCurrentValue[47]  =  FM_CPU1_DAM_R_LVC18          ; //    pin rjo #20 address = 0xC8  // inout

 
 assign wPD_CPU0_TXT_PLTEN_RJC        =  wOvEnable_n  [1 ] ? PD_CPU0_TXT_PLTEN_RJC           :  wOverrideValue[1 ];// pin rjo #1  address = 0x10  // inout 
 assign wPD_CPU1_TXT_PLTEN_RJC        =  wOvEnable_n  [2 ] ? PD_CPU1_TXT_PLTEN_RJC           :  wOverrideValue[2 ];// pin rjo #2  address = 0x14  // inout 
 assign wPD_CPU0_BIST_ENABLE_RJC      =  wOvEnable_n  [3 ] ? PD_CPU0_BIST_ENABLE_RJC         :  wOverrideValue[3 ];// pin rjo #3  address = 0x18  // inout 
 assign wPD_CPU1_BIST_ENABLE_RJC      =  wOvEnable_n  [4 ] ? PD_CPU1_BIST_ENABLE_RJC         :  wOverrideValue[4 ];// pin rjo #4  address = 0x1C  // inout 
 assign wFM_BIOS_IMAGE_SWAP_RJC       =  wOvEnable_n  [5 ] ? FM_BIOS_IMAGE_SWAP_RJC          :  wOverrideValue[5 ];// pin rjo #5  address = 0x20
 assign wFM_FORCE_PWRON_MODE1_LVC3    =  wOvEnable_n  [6 ] ? FM_FORCE_PWRON_MODE1_LVC3       :  wOverrideValue[6 ];// pin rjo #6  address = 0x24              
 assign wFM_FORCE_PWRON_MODE2_LVC3    =  wOvEnable_n  [7 ] ? FM_FORCE_PWRON_MODE2_LVC3       :  wOverrideValue[7 ];// pin rjo #7  address = 0x28      
 assign wFM_S5_WITH_12V_RJC_N         =  wOvEnable_n  [8 ] ? FM_S5_WITH_12V_RJC_N            :  wOverrideValue[8 ];// pin rjo #8  address = 0x2C     
 assign wP3V3_BAT_SOURCE_RJC          =  wOvEnable_n  [9 ] ? P3V3_BAT_SOURCE_RJC             :  wOverrideValue[9 ];// pin rjo #9  address = 0x30 // only read
 assign wFM_CPU0_SKTOCC_RJC_N         =  wOvEnable_n  [10] ? FM_CPU0_SKTOCC_RJC_N            :  wOverrideValue[10];// pin rjo #10 address = 0x34 // only read
 assign wFM_CPU1_SKTOCC_BP            =  wOvEnable_n  [11] ? FM_CPU1_SKTOCC_BP               :  wOverrideValue[11];// pin rjo #11 address = 0x38 // only read
 assign wFP_CHASSIS_INTRUSION_RJC     =  wOvEnable_n  [12] ? FP_CHASSIS_INTRUSION_RJC        :  wOverrideValue[12];// pin rjo #12 address = 0x3C  // inout 
 assign wFM_OCP_PERST_TIMING_SEL_LVC3 =  wOvEnable_n  [13] ? FM_OCP_PERST_TIMING_SEL_LVC3    :  wOverrideValue[13];// pin rjo #13 address = 0x40
 assign wFM_CPU0_TXT_AGENT_LVC1       =  wOvEnable_n  [14] ? FM_CPU0_TXT_AGENT_LVC1          :  wOverrideValue[14];// pin rjo #14 address = 0x44  // inout 
 assign wFM_CPU1_TXT_AGENT_LVC1       =  wOvEnable_n  [15] ? FM_CPU1_TXT_AGENT_LVC1          :  wOverrideValue[15];// pin rjo #15 address = 0x48  // inout 
 assign wPU_CPU0_SAFE_MODE_BOOT_RJC   =  wOvEnable_n  [16] ? PU_CPU0_SAFE_MODE_BOOT_RJC      :  wOverrideValue[16];// pin rjo #16 address = 0x4C  // inout 
 assign wPU_CPU1_SAFE_MODE_BOOT_RJC   =  wOvEnable_n  [17] ? PU_CPU1_SAFE_MODE_BOOT_RJC      :  wOverrideValue[17];// pin rjo #17 address = 0x50  // inout 
 assign wFM_PMBUS2_MUX_SEL_FPGA       =  wOvEnable_n  [18] ? FM_PMBUS2_MUX_SEL_FPGA          :  wOverrideValue[18];// pin rjo #18 address = 0x54
 assign wFM_CPU0_DAM_R_LVC18          =  wOvEnable_n  [46] ? FM_CPU0_DAM_R_LVC18             :  wOverrideValue[46];// pin rjo #46 address = 0x58
 assign wFM_CPU1_DAM_R_LVC18          =  wOvEnable_n  [47] ? FM_CPU1_DAM_R_LVC18             :  wOverrideValue[47];// pin rjo #47 address = 0x5C
 
 assign PD_CPU0_TXT_PLTEN_RJC        =  wOvEnable_n  [1 ] ? 1'bZ :  wOverrideValue[1 ];// pin rjo #1  address = 0x10  // inout 
 assign PD_CPU1_TXT_PLTEN_RJC        =  wOvEnable_n  [2 ] ? 1'bZ :  wOverrideValue[2 ];// pin rjo #2  address = 0x14  // inout 
 assign PD_CPU0_BIST_ENABLE_RJC      =  wOvEnable_n  [3 ] ? 1'bZ :  wOverrideValue[3 ];// pin rjo #3  address = 0x18  // inout 
 assign PD_CPU1_BIST_ENABLE_RJC      =  wOvEnable_n  [4 ] ? 1'bZ :  wOverrideValue[4 ];// pin rjo #4  address = 0x1C  // inout  
 assign FP_CHASSIS_INTRUSION_RJC     =  wOvEnable_n  [12] ? 1'bZ :  wOverrideValue[12];// pin rjo #12 address = 0x3C  // inout
 assign FM_CPU0_TXT_AGENT_LVC1       =  wOvEnable_n  [14] ? 1'bZ :  wOverrideValue[14];// pin rjo #14 address = 0x44  // inout
 assign FM_CPU1_TXT_AGENT_LVC1       =  wOvEnable_n  [15] ? 1'bZ :  wOverrideValue[15];// pin rjo #15 address = 0x48  // inout
 assign PU_CPU0_SAFE_MODE_BOOT_RJC   =  wOvEnable_n  [16] ? 1'bZ :  wOverrideValue[16];// pin rjo #16 address = 0x4C  // inout
 assign PU_CPU1_SAFE_MODE_BOOT_RJC   =  wOvEnable_n  [17] ? 1'bZ :  wOverrideValue[17];// pin rjo #17 address = 0x50  // inout
 assign FM_CPU0_DAM_R_LVC18          =  wOvEnable_n  [46] ? 1'bZ :  wOverrideValue[46];// pin rjo #46 address = 0x58 
 assign FM_CPU1_DAM_R_LVC18          =  wOvEnable_n  [47] ? 1'bZ :  wOverrideValue[47];// pin rjo #47 address = 0x5C 

assign owOverrideValue_14 = wOverrideValue[14];
assign owOverrideValue_15 = wOverrideValue[15];

pca9555 #(.DEVICE_ADDR(7'h40),// 0x40 in 8bit format
             .P_RV_CONFIG0(8'h00)   //Register CONFIG0 reset value defined to have all bits as outputs
             )
   
exp0_Bifurcation   // I/O Expander number 0 for Biffurcation
     (
      .iClk       (wClk_20M                ),
      .iRst_n     (wRst_n                  ),
      .iSCL       (SMB_HOST_SECFPGA_SCL    ),
      .ioSDA      (SMB_HOST_SECFPGA_SDA    ),
                   
      .ioDataP0 ({  bidin[7],           //  P0.B7 FM_PCIE_BIF_CPU_3
                    bidin[6],           //  P0.B6 FM_PCIE_BIF_CPU_2  
                    bidin[5],           //  P0.B5 FM_PCIE_BIF_CPU_1     
                    bidin[4],           //  P0.B4 FM_PCIE_BIF_CPU_0        
                    bidin[3],           //  P0.B3 FM_PCIE_BIF_PORT_3      
                    bidin[2],           //  P0.B3 FM_PCIE_BIF_PORT_2   
                    bidin[1],           //  P0.B3 FM_PCIE_BIF_PORT_1     
                    bidin[0]} ),        //  P0.B3 FM_PCIE_BIF_PORT_0       
      .ioDataP1   (),         //port1 not in use
      .oSmbAlert_n()
      );

reg rmod_rp;
reg[1:0] rriser_width_mode;

always @(posedge wClk_20M) begin
   rmod_rp<=wIsModular;  // Select rp o modular value for bifurcation platform select.
  
   case ( bidin  )
        8'b0000_0000: rriser_width_mode<= {wFM_CPU0_LEFT_RISER_WIDTH_LVC18_N    ,  wFM_CPU0_LEFT_RISER_MODE_LVC18_N     };
        8'b0000_0001: rriser_width_mode<= {                1'bx                 ,  wF0M_CPU0_EDSFFX4_EXPCARD_IO0_LVC3_R };
        8'b0000_0010: rriser_width_mode<= {wFM_CPU0_LEFT_RISER_WIDTH_LVC18_N    ,  wFM_CPU0_LEFT_RISER_MODE_LVC18_N     };
        8'b0000_0011: rriser_width_mode<= {wFM_CPU0_LEFT_RISER_WIDTH_LVC18_N    ,  wFM_CPU0_LEFT_RISER_MODE_LVC18_N     };
        8'b0000_0100: rriser_width_mode<= {                1'bx                 ,               1'bx                    };
        8'b0000_0101: rriser_width_mode<= {                1'bx                 ,               1'bx                    };
               
        8'b0001_0000: rriser_width_mode<= {wFM_CPU1_RIGHT_RISER_WIDTH_LVC18     ,  wFM_CPU1_RIGHT_RISER_MODE_LVC18_N    };
        8'b0001_0001: rriser_width_mode<= {                1'bx                 ,               1'bx                    };
        8'b0001_0010: rriser_width_mode<= {wFM_CPU1_RIGHT_RISER_WIDTH_LVC18     ,  wFM_CPU1_RIGHT_RISER_MODE_LVC18_N    };
        8'b0001_0011: rriser_width_mode<= {                1'bx                 ,  FM_CPU1_PE3_MISC_MUX_SEL             };
        8'b0001_0100: rriser_width_mode<= {                1'bx                 ,               1'bx                    };
        8'b0001_0101: rriser_width_mode<= {                1'bx                 ,               1'bx                    };
  endcase
end

wire wRP_MOD_N ;
wire wRISER_MODE_N; 
wire wRISER_WIDTH ;  

reg enable_mod_rp=1;
assign wRP_MOD_N     = enable_mod_rp ? rmod_rp             :'bz;
assign wRISER_MODE_N = enable_mod_rp ? rriser_width_mode[0]:'bz;
assign wRISER_WIDTH  = enable_mod_rp ? rriser_width_mode[1]:'bz;

reg enable_out = 1'b1;
wire [7:0] dataout;
assign dataout[7:0] = enable_out ? bidout [7:0] : 'bz;

pca9555 #(
         .DEVICE_ADDR    (7'h42), // 0x42 in 8bit format
         .P_RV_CONFIG0   (8'hFF) ,  //Register CONFIG0 reset value defined to have all bits as inputs
			.P_RV_CONFIG1   (8'hff)   //Register CONFIG0 reset value defined to have all bits as inputs
        )
 
       
exp1_Bifurcation   // I/O Expander number 1 for Biffurcation
    (
     .iClk     ( wClk_20M             ),
     .iRst_n   ( wRst_n               ),
     .iSCL     ( SMB_HOST_SECFPGA_SCL ),
     .ioSDA    ( SMB_HOST_SECFPGA_SDA ),
     .ioDataP0 ({  FM_PCIE_FV_BIF_EN ,  //  P0.B7 FM_PCIE_FV_BIF_EN
                   resv ,               //  P0.B6 RSVD  
                   resv ,               //  P0.B5 RSVD     
                   dataout[4],          //  P0.B4 FM_PCIE_BIF_BIT_4        
                   dataout[3],          //  P0.B3 FM_PCIE_BIF_BIT_3      
                   dataout[2],          //  P0.B2 FM_PCIE_BIF_BIT_2
                   dataout[1],          //  P0.B1 FM_PCIE_BIF_BIT_1  
                   dataout[0]} ),       //  P0.B0 FM_PCIE_BIF_BIT_0               
										
										
   .ioDataP1 ( {  wRP_MOD_N,            //  P1.B7 RP_MOD_N //rp =0 modular=1
                  resv,                 //  P1.B6 RSVD  
                  resv,                 //  P1.B5 RSVD     
                  resv,                 //  P1.B4 RSVD     
                  wRISER_MODE_N,        //  P1.B3 RISER_MODE_N    
                  wRISER_WIDTH,         //  P1.B2 RISER_WIDTH
                  dataout[5],           //  P1.B1 HSBP_MODE  
                  dataout[6]}),         //  P1.B0 HSBP_WIDTH   

     .oSmbAlert_n()
     );

// This module drive to jumper overr
RJO_TOP 

  #(
        .JUMPER_COUNT  (JUMPER_COUNT) 
   
    )RJO_TOP_inst
(
     .Clock                             ( wClk_20M                           ),
     .Reset                             ( !wRst_n                            ), 
     .FM_VAL_DBG_JUMPER_EN              ( FM_VAL_DBG_JUMPER_EN_N             ),
     .T_Reset                           ( T_Reset                            ), 
     .iPLTRST_N                         ( wPLTRST_N                          ), 
     .iSlpS3                            ( wSlpS3                             ),
     .iAUX_PWRGD_CPU                    ( wAUX_PWRGD_CPU                     ),
     .JumperOut                         ( wOverrideValue                     ), 
	  .JumperIn                          ( wCurrentValue                     ),
     .iCPU0_MEM_Done                    ( iCPU0_MEM_Done                     ),    
     .iCPU1_MEM_Done                    ( iCPU1_MEM_Done                     ), //AVMM master      
     .RSU_FlashBusy                     (     1'b0          ),  
     .invalid_access                    ( invalid_access_rjo                 ), 
     .FM_TTK_SPI_EN_RJC_N_Override      ( FM_TTK_SPI_EN_RJC_N_Override       ),
	  .PFR_DEBUG_JUMPER_RJC_N_Override   ( PFR_DEBUG_JUMPER_RJC_N_Override    ),
	  .PFR_FORCE_RECOVERY_RJC_N_Override ( PFR_FORCE_RECOVERY_RJC_N_Override  ),
	  .FM_TTK_SPI_EN_RJC_N_Value         ( FM_TTK_SPI_EN_RJC_N_Value          ),
	  .PFR_DEBUG_JUMPER_RJC_N_Value      ( PFR_DEBUG_JUMPER_RJC_N_Value       ),
	  .PFR_FORCE_RECOVERY_RJC_N_Value    ( PFR_FORCE_RECOVERY_RJC_N_Value     ),	  
     // Interface conected to mux avmm_mux_1to2
     .avmm_address                      ( RJO_csr_address                    ),     
     .avmm_writedata                    ( RJO_csr_writedata                  ),
     .avmm_write                        ( RJO_csr_write                      ), 
     .avmm_read                         ( RJO_csr_read                       ),       
     .avmm_readvalid                    ( RJO_csr_readdatavalid              ), 
     .avmm_readdata                     ( RJO_csr_readdata                   ),  
     .avmm_waitrequest                  ( RJO_csr_waitrequest                ), 
     .avmm_byteenable                   ( RJO_csr_byteenable                 ),
         
     .avmm_csr_addr                     ( RJO_flash_csr_addr                 ),     
     .avmm_csr_read                     ( RJO_flash_csr_read                 ),
     .avmm_csr_writedata                ( RJO_flash_csr_writedata            ), 
     .avmm_csr_write                    ( RJO_flash_csr_write                ),       
     .avmm_csr_readdata                 ( RJO_flash_csr_readdata             ), 
     .avmm_data_addr                    ( RJO_flash_data_addr                ),  
     .avmm_data_read                    ( RJO_flash_data_read                ), 
     .avmm_data_writedata               ( RJO_flash_data_writedata           ),
     .avmm_data_write                   ( RJO_flash_data_write               ),  
     .avmm_data_readdata                ( RJO_flash_data_readdata            ), 
     .avmm_data_waitrequest             ( RJO_flash_data_waitrequest         ),      
     .avmm_data_readdatavalid           ( RJO_flash_data_readdatavalid       ), 
     .avmm_data_burstcount              ( RJO_flash_data_burstcount          ),         
     .oOvDisable                        ( wOvEnable_n                        ), 
     .rjo_ready                         ( wSMRJODone                         ),
	  .bidin                             ( bidin                              ),
	  .bidout                            ( bidout                              )
   );




//Instantiate Internal Flash

   secondary_flash  secondary_flash_inst
   (
       .clock                    ( wClk_20M                    ),
       .reset_n                  ( wRst_n                      ),
       .avmm_csr_addr            ( RJO_flash_csr_addr          ),
       .avmm_csr_read            ( RJO_flash_csr_read          ),
       .avmm_csr_writedata       ( RJO_flash_csr_writedata     ),
       .avmm_csr_write           ( RJO_flash_csr_write         ),
       .avmm_csr_readdata        ( RJO_flash_csr_readdata      ),
       .avmm_data_addr           ( RJO_flash_data_addr[16:0]   ),
       .avmm_data_read           ( RJO_flash_data_read         ),
       .avmm_data_writedata      ( RJO_flash_data_writedata    ),
       .avmm_data_write          ( RJO_flash_data_write        ),
       .avmm_data_readdata       ( RJO_flash_data_readdata     ),
       .avmm_data_waitrequest    ( RJO_flash_data_waitrequest  ),
       .avmm_data_readdatavalid  ( RJO_flash_data_readdatavalid),
       .avmm_data_burstcount     ( RJO_flash_data_burstcount   )  
   );




secondary_global_csr    secondary_global_csr_inst
(
    .clk                ( wClk_20M                      ),
    .reset              ( !wRst_n                       ),
    //avmm interface                                
    .avmm_address       ( secondary_csr_address         ),
    .avmm_write         ( secondary_csr_write           ),
    .avmm_writedata     ( secondary_csr_writedata       ),          
    .avmm_read          ( secondary_csr_read            ),     
    .avmm_readdata      ( secondary_csr_readdata        ),      
    .avmm_readdatavalid ( secondary_csr_readdatavalid   ), 
    .avmm_waitrequest   ( secondary_csr_waitrequest     ),           
    .avmm_byteenable    ( secondary_csr_byteenable      ),
    .invalid_access     ( invalid_access_glb            ),
    .ihp_slot_led       ({LED_HP_SLOTB_PWR, LED_HP_SLOTB_ATTN, LED_HP_SLOTC_PWR, LED_HP_SLOTC_ATTN}),
	.bios_postcode      ( wBiosPostCode             )
);

// Synchronize to 20 MHz clock domain
InputsSyncWithDefault # (   
   .SIZE       ( 3'd2 ),
   .DEFAULT_OUT( 1'b0 )
) InputsSyncWithDefault_U0 (   
   .i_Clk  ( wClk_20M ),
   .i_Rst_n( wRst_n ), 
   .i_vSync({
      
       SMB_MAIN_DBG_MM_SCL,
       SMB_MAIN_DBG_MM_SDA
   }),
   .o_vSync({
      i2c_dbg_clk_in ,
      i2c_dbg_data_in 
       
   }) 
);


endmodule // BncSecondaryTop
